The present invention relates to semiconductor design technologies; and, more particularly, to a semiconductor memory device which is provided with an internal power generator capable of increasing a cell retention time during a self refresh mode and a refresh unit capable of minimizing power consumption by adjusting a refresh period depending on a level of an internal power.
Generally, basic operations of a semiconductor memory device include a write operation for storing data provided from outside and a read operation for outputting desired data stored therein upon request from the outside. In order to perform these write and read operations, the semiconductor memory device requires the capability of storing data from the outside.
In particular, since DRAM (Dynamic Random Access Memory) is a nonvolatile memory, data stored therein is lost after a fixed amount of time elapses. Therefore, a refresh operation is needed to fully restore data stored in memory cells before the fixed amount of time in order to prevent the loss of data. This refresh operation has priority over any other operations in DRAM.
Such a refresh operation is done at a fixed period that is closely concerned with a retention time of cell data. More details on this will be given below with reference to a circuit and a cross-sectional view of unit memory cell.
FIG. 1A is a conceptual circuit diagram of unit memory cell of a conventional DRAM. For reference, the unit memory cell denotes a space where 1 bit data is stored.
Referring to FIG. 1A, the unit memory cell is provided with a capacitor C1 for storing data and an NMOS transistor NM1 for accessing the capacitor.
To be more specific, a word line WL is connected to the gate end of the NMOS transistor NM1. And, a bit line BL is connected to one side active region (here, a drain end) of the NMOS transistor NM1 and the cell capacitor to other side active region (here, a source end) thereof.
FIG. 1B is a cross-sectional view of the unit memory cell of FIG. 1A, and particularly shows a leakage current generated in the unit memory cell.
As shown in FIG. 1B, although the transistor is turned off, a leakage current occurs in the cell capacitor (here, it is assumed that logic high data is stored in the cell capacitor). Two major factors of the leakage current are an off current IOFF and a junction current IJUN.
Meanwhile, an internal power VBB with a negative electric potential lower than a ground voltage is generally connected to a bulk of the NMOS transistor in the unit memory cell shown in FIG. 1A. By keeping the bulk bias low like this, the leakage current as shown in FIG. 1B is reduced by setting a threshold voltage of the transistor higher than that of a general NMOS. But, as the level of the internal power VBB lowers, the threshold voltage becomes higher to decrease off-current, while rather increasing the leakage current by elevation of junction-current. That is, the off-current and the junction-current constituting the leakage current have a trade-off relationship depending on the level of the internal power VBB. Therefore, in order to extend a retention time of cell data, it is important to find an optimal level of the internal power VBB making both the off-current and the junction-current smaller.
The following is a description for a conventional internal power generator for generating an internal power VBB to be applied to a bulk end of cell and a refresh unit for refreshing cell data.
FIG. 2 is a block diagram showing a configuration of a conventional internal power generator.
Referring to FIG. 2, the conventional internal power generator includes a charge pumping circuit 40 for negative-pumping an external power VDD to generate an internal power VBB with a level lower than the external power VDD, a reference voltage generator 50 for producing a reference voltage VINT_BB, a level sensor 10 for sensing a level of the internal power VBB on the basis of the reference voltage VINT_BB, an oscillator 20 for generating a period signal OSC in response to a sensing signal BBE of the level sensor 10, and a pumping control signal generator 30 for controlling the operation of the charge pumping circuit 40 in response to the period signal OSC.
The reference voltage generator 50 is provided with a voltage generator 52 for generating a target voltage of the internal power VBB and a level shifter 54 for level-shifting an output voltage VREF of the voltage generator 52 to generate the reference voltage VINT_BB having a stable level regardless of the external power VDD (or power supply voltage).
FIG. 3 illustrates an internal circuit diagram of the level sensor 10 of FIG. 2.
Referring to FIG. 3, the level sensor 10 is composed of a voltage divider 12 for voltage-dividing a level difference between the ground voltage VSS and the reference voltage VINT_BB by a level difference between the ground voltage VSS and the internal power VBB, an inverter 14 for taking the reference voltage VINT_BB and the ground voltage VSS as driving powers and inverting and outputting an output voltage of the voltage divider 12, a differential amplifier 16 taking an output voltage of the inverter 14 and an inverted voltage of the output of the inverter 14 as differential inputs, and an inverter I1 for inverting an output voltage of the differential amplifier 16 to provide an inverted voltage as the sensing signal BBE.
Hereinafter, the operation of the internal power generator shown in FIGS. 2 and 3 will be briefly described.
First, the level sensor 10 senses a level of a feedbacked internal power VBB on the basis of the reference voltage VINT_BB. At this time, when the level of the internal power VBB is higher than the reference voltage VINT_BB and the output voltage of the voltage divider 12 exceeds a logic threshold voltage of the inverter 14, the sensing signal BBE is activated to a logic high level.
Then, the oscillator 20 is active by the sensing signal BBE to create the period signal OSC. In response to the period signal OSC, the pumping control signal generator 30 drives the charge pumping circuit 40, which causes the level of the internal power VBB to drop.
When the level of the internal power VBB drops, the output voltage of the voltage divider 12 becomes lower than the logic threshold voltage of the inverter 14 which makes the sensing signal BBE inactivated to a logic low level.
Thus, the operations of the oscillator 20, the pumping control signal generator 30 and the charge pumping circuit 40 are closed.
As described above, the internal power generator in the conventional semiconductor memory device is driven to maintain the internal power VBB in a level corresponding to the target level of the reference voltage. Here, as mentioned above, the level of the reference voltage is set such that the operation such as storage of data in write operation or restoration of data in read operation can be made within a designated time, while securing the retention time of data by reduction in leakage current. For reference, in order to secure the retention time of data, it is preferred that the level of the internal power VBB is as low as possible. But, if the level of the internal power VBB becomes lower, the threshold voltage becomes higher, which prolongs the operation time of data storage or restoration.
However, the conventional internal power generator is driven without considering IDD6 circumstance capable of securing a greater margin than an active mode as a driving time for restoration of data. That is, it was impossible to control the retention time of cell data to be extended for the refresh interval.
For reference, the IDD6 circumstance is a mode that is entered when the clock enable signal CLK is transited to a logic low level and again stores all cells by performing 8K number of times of refreshes for 64 ms.
FIG. 4 is a block diagram showing a configuration of a refresh unit included in the conventional semiconductor memory device.
Referring to FIG. 4, the conventional refresh unit includes a mode input/output controller 60 for accepting a clock enable signal CKE and an auto refresh command AREF_CMD and generating an internal auto refresh signal AREFP, a self refresh entry signal SREF_EN and a self refresh escape signal SREF_EXP, a refresh interval signal generator 70 for generating a self refresh interval signal SREF notifying a self refresh interval by using the internal auto refresh signal AREFP, the self refresh entry signal SREF_EN and the self refresh escape signal SREF_EXP, a refresh period signal generator 80 for periodically outputting a period-pulse signal PL_FLG during activation of the self refresh interval signal SREF, an internal refresh signal generator 90 for activating an internal refresh signal REFP in response to the internal auto refresh signal AREFP and the period-pulse signal PL_FLG, and an internal address counter 95 for increasing a row address by one bit unit in response to the internal refresh signal REFP to output an internal address RCNTI[0:N].
For reference, the clock enable signal CKE is a signal representing whether a clock synchronizing the operation of the semiconductor memory device is valid or not. Thus, if only the clock enable signal CKE is inactivated, the semiconductor memory device enters a power-down mode for minimizing its own power consumption.
FIG. 5 shows an internal circuit diagram of the refresh period signal generator 80 of FIG. 4.
Referring to FIG. 5, the refresh period signal generator 80 includes an oscillator 82 which has an inverter chain and is active upon activation of the self refresh interval signal SREF to generate a signal OSC_OUT at regular intervals, and a pulse generator 84 for producing the period-pulse signal PL_FLG of pulse type from the output signal OSC_OUT of the oscillator 82.
In brief operation, first of all, when the self refresh interval signal SREF is activated to a logic high level, the oscillator 82 generates the signal OSC_OUT at a regular interval. Here, the regular intervals are determined based on the voltage levels of signals applied to the gate ends of NMOS transistors and PMOS transistors constituting the inverter chain. Next, the pulse generator 84 senses a rising edge of the output signal OSC_OUT of the oscillator 82, and generates the period-pulse signal PL_FLG of pulse type.
FIG. 6 presents an operational waveform diagram of the refresh unit according to the prior art shown in FIGS. 4 and 5.
As shown in FIG. 6, the clock enable signal CKE is first transited to a logic low level and at the same time the auto refresh command AREF_CMD is activated. Then, the mode input/output controller 60 activates the self refresh entry signal SREF_EN in response to the logic level transition of the clock enable signal CKE and activates the internal auto refresh signal AREFP in response to the auto refresh command AR.
Next, the internal refresh signal generator 90 generates the internal refresh signal REFP in response to the internal auto refresh signal AREFP. In succession, the internal address generator 95 increases the row address by one bit unit whenever the internal refresh signal REFP is activated, to output the internal address RCNTI[0:N].
Further, the refresh interval signal generator 70 activates the self refresh interval signal SREF in response to activation of the internal auto refresh signal AREFP and the self refresh entry signal SREF_EN, wherein this activation is maintained until the self refresh escape signal SREF_EXP is applied.
Subsequently, the refresh period signal generator 80 periodically activates the period-pulse signal PL_FLG during the activation of the self refresh interval signal SREF. And then, the internal refresh signal generator 90 activates a new internal refresh signal REFP of pulse type whenever the period-pulse signal PL_FLG is applied. Lastly, the internal address generator 95 increases the row address by one bit unit whenever the internal refresh signal REFP is activated, to output the internal address RCNTI[0:N].
For reference, the internal refresh signal REFP is applied to each bank, which makes a word line corresponding to the internal address RCNTI[0:N] active to perform self refresh.
Meanwhile, the refresh period by the refresh unit in the conventional semiconductor memory device is determined by the period of the period-pulse signal PL_FLG. The period-pulse signal PL_FLG is generated at a regular period, regardless of the level of the internal power VBB. Therefore, although the level of the internal power VBB is optimized so that the retention time is reduced, it is unlikely to reflect the above. This reduces the number of times of refresh and thus cannot decrease power consumption.
Therefore, the conventional semiconductor memory device does not adjust the level of the internal power under the self refresh mode, thereby making it impossible to adjust the retention time of cell data. Also, the refresh unit cannot be driven appropriately according to the retention time.